Fault modeling and parametric fault detection in analog VLSI circuits using discretization

@article{Raj2019FaultMA,
  title={Fault modeling and parametric fault detection in analog VLSI circuits using discretization},
  author={Baldev Raj and Ghulam Mohiuddin Bhat and Sandeep Kumar Thakur},
  journal={International Journal of Electrical and Computer Engineering},
  year={2019},
  volume={9},
  pages={1598-1605}
}
In this article we describe new model for determination of fault in circuit and also we provide detailed analysis of tolerance of circuit, which is considered one of the important parameter while designing the circuit. We have done mathematical analysis to provide strong base for our model and also done simulation for the same. This article describes detailed analysis of parametric fault in analog VLSI circuit. The model is tested for different frequencies for compactness and its flexibility… Expand

References

SHOWING 1-10 OF 22 REFERENCES
Diagnosis of parametric faults in linear analog VLSI circuits
TLDR
The whole method for testing of linear analog VLSI circuits and this approach is tested on two analog circuits, integrator circuit and MIMO circuit. Expand
Multiple fault analog circuit testing by sensitivity analysis
TLDR
Using this approach, adequate tests are identified for testing catastrophic and soft faults and some experimental results are presented for simple models as well as multiple-fault models. Expand
A novel approach for calculation of component tolerance in analog VLSI circuits using ISFG technique
  • S. Thakur, Abishek Naithani
  • Computer Science
  • 2016 Online International Conference on Green Engineering and Technologies (IC-GET)
  • 2016
TLDR
A new approach for calculation of component tolerance which is based on signal flow graph (SFG) which is applicable to various types of analog VLSI circuits is proposed. Expand
Detection of catastrophic faults in analog integrated circuits
  • L. Milor, V. Visvanathan
  • Engineering, Computer Science
  • IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
  • 1989
TLDR
The construction of a set of measurements that detects many faulty circuits before specification testing is described, and its effectiveness in detecting faulty circuits is evaluated. Expand
Minimizing production test time to detect faults in analog circuits
TLDR
Algorithms for fault-driven test set selection are presented based on an analysis of the types of tests needed for different types of faults, and a major reduction in testing time should come from reducing the number of specification tests that need to be performed. Expand
Symbolic sensitivity analysis in the sizing of analog integrated circuits
TLDR
A graph-based symbolic technique is presented for deriving analytical expressions for differential gain, common-mode gain and then common- mode rejection ratio (CMRR) of operational transconductance amplifiers (OTAs) and a comparison between the derived symbolic expressions and HSpice simulations is made to show that the circuit elements causing large sensitivities implies large performance variations. Expand
Analog and mixed-signal benchmark circuits-first release
TLDR
A set of typical circuits described by netlists in HSPICE format is presented, which will allow engineers and researchers working in analog and mixed-signal testing to compare test results as is done in the digital domain. Expand
Concurrent Error Detection in Linear Analog and Switched-Capacitor State Variable Systems Using Continuous Checksums
TLDR
This paper studies the problem of concurrent error detection in analog and switched-capacitor state variable systems by using continuous matrix chechums for error detection. Expand
Checksum-based concurrent error detection in linear analog systems with second and higher order stages
  • A. Chatterjee
  • Mathematics, Computer Science
  • Digest of Papers. 1992 IEEE VLSI Test Symposium
  • 1992
TLDR
The problem of concurrent error detection in a class of linear analog systems containing second and higher order stages is discussed in this paper and a small amount of additional hardware is used to perform error detection. Expand
Test Vector Generation for Linear Analog Devices
  • S. Tsai
  • Computer Science
  • 1991, Proceedings. International Test Conference
  • 1991
TLDR
The vector generation task is formulated as a quadratic programming problem, and an innovative algorithm is developed to provide the solution, and results using a bandpass filter as an example are presented. Expand
...
1
2
3
...