Fault-aware configurable logic block for reliable reconfigurable FPGAs

  title={Fault-aware configurable logic block for reliable reconfigurable FPGAs},
  author={B. Chagun Basha and S{\'e}bastien Pillement and Stanislaw J. Piestrak},
  journal={2015 IEEE International Symposium on Circuits and Systems (ISCAS)},
Field Programmable Gate Arrays (FPGAs) used in mission-critical applications such as aerospace, nuclear, and defense require high reliability in spite of internal faults. Fortunately, today's FPGAs have the ability to dynamically reconfigure themselves in the field, which may help to mitigate the effects of certain faults affecting the FPGA devices. Although the reconfiguration process can remove only the upsets affecting the configuration bitstream, unfortunately, there are other sources of… CONTINUE READING

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Xilinx 7 Series FPGAs: The logical advantage, Xilinx

  • N. Mehta
  • White Paper WP405 (v1.0),
  • 2012
Highly Influential
11 Excerpts

Correcting single-event upsets in Virtex-4 FPGA configuration memory

  • C. Carmichael, C. W. Tseng
  • Xilinx Appl. Note XAPP1088 (v1.0), 5 Oct. 2009.
  • 2009
2 Excerpts

Single-event upset mitigation selection guide

  • B. Bridgford, C. Carmichael, C. W. Tseng
  • Xilinx Appl. Note XAPP987 (v1.0), 18 March 2008.
  • 2008
1 Excerpt

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