Corpus ID: 32543870

Fault Tolerant Synthesis of Reversible Circuits

  title={Fault Tolerant Synthesis of Reversible Circuits},
  author={Anugrah Jain},
Reversible computing has emerged as a possible low cost alternative to conventional computing in terms of speed, power consumption and computing capability. In order to achieve reliable circuits in reversible computing, provision for fault tolerance is necessary. A number of fault models, fault tolerant techniques (such as parity-preserving) and testing approaches have proposed in literature. This dissertation exploits parity-preserving characteristics of two reversible gates which provide low… Expand
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A Novel Fault Tolerant Reversible Gate For Nanotechnology Based Systems
This paper proposes a novel reversible logic gate, NFT. It is a parity preserving reversible logic gate, that is, the parity of the outputs matches that of the inputs. We demonstrate that the NFTExpand
Fault testing for reversible circuits
It is shown that any test set that detects all single stuck-at faults in a reversible circuit also detects all multiple stuck- at faults, and a practical test-set generation algorithm is given, based on an integer linear programming formulation, that yields test sets approximately half the size of those produced by conventional automatic test pattern generation. Expand
Fault-Tolerant Reversible Circuits
  • B. Parhami
  • Computer Science
  • 2006 Fortieth Asilomar Conference on Signals, Systems and Computers
  • 2006
A class of reversible logic gates is introduced (consisting of the well-known Fredkin gate and a newly defined Feynman double-gate) for which the parity of the outputs matches that of the inputs that allow any fault that affects no more than a single logic signal to be detectable at the circuit's primary outputs. Expand
Testing for missing-gate faults in reversible circuits
A new fault model, the missing gate fault (MGF) model, is proposed to better represent the physical failure modes of quantum technologies and it is shown that MGFs are highly testable, and that all M GFs in an N-gate k-CNOT circuit can be detected with from one to [N/2] test vectors. Expand
On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set
It is shown that in an (n times n) reversible circuit implemented with k-CNOT gates, addition of only one extra control line along with duplication each k- CNOT gate yields an easily testable design, which admits a universal test set of size (n +1) that detects all SMGFs, R GFs, and PMGFs in the circuit. Expand
Designing Efficient Online Testable Reversible Adders With New Reversible Gate
  • H. Thapliyal, A. P. Vinod
  • Computer Science, Mathematics
  • 2007 IEEE International Symposium on Circuits and Systems
  • 2007
A new 4 times 4 reversible gate termed `OTG' (online testable gate) is proposed suitable for online testability in reversible logic circuits and is shown better than the recently proposed R1 gate, in terms of computation complexity. Expand
Reversible-logic design with online testability
This paper proposes three new reversible logic gates; two of the proposed gates can be employed to design online testable reversible logic circuits and can be used to implement any Boolean logic function. Expand
Synthesis of reversible logic circuits
In an application important to quantum computing, the synthesis of oracle circuits for Grover's search algorithm are synthesized, and a significant improvement over a previously proposed synthesis algorithm is shown. Expand
BDD-based synthesis of reversible logic for large functions
  • R. Wille, R. Drechsler
  • Computer Science, Mathematics
  • 2009 46th ACM/IEEE Design Automation Conference
  • 2009
This paper presents a technique to derive reversible circuits for a function given by a binary decision diagram (BDD), and shows better results and a significantly better scalability in comparison to previous synthesis approaches. Expand
Online fault testing of reversible logic using dual rail coding
A set of novel dual rail reversible logic gates for online testable reversible logic design that detects 100% of single faults while reducing the area and the number of garbage outputs up to 6.4X and 4.6X, compared to previously proposed techniques, respectively. Expand