• Corpus ID: 10451667

Fault Tolerance Technique for DynamicallyReconfigurable Processor

@article{Mathew2014FaultTT,
  title={Fault Tolerance Technique for DynamicallyReconfigurable Processor},
  author={Julia Mathew and R.Dhayabarani},
  journal={International Journal of Advanced Research in Electrical, Electronics and Instrumentation Energy},
  year={2014},
  volume={3},
  pages={6656-6663}
}
  • Julia Mathew, R.Dhayabarani
  • Published 2014
  • Computer Science
  • International Journal of Advanced Research in Electrical, Electronics and Instrumentation Energy
This paper proposes a new technique to detect and eliminates temporary faults on FPGA systems. Soft core processors which can alleviate radiation induced failures is implemented on Virtex-5 FPGA’s. This Fault tolerant technique is implemented using TMR .It recovers from configuration upsets through partial reconfiguration combined with roll-forward recovery .The lockstep scheme used here eliminates configuration upsets without interrupting normal functioning. Main Significance includes less… 
On providing scalable self-healing adaptive fault-tolerance to RTR SoCs
TLDR
The presented system demonstrates the feasibility of the Upset-Fault-Observer concept, which provides a run-time self-test and recovery strategy that delivers fault-tolerance over functions accelerated in RTR cores, at the same time reducing the redundancy scalability cost by running periodic reconfigurable TMR scan-cycles.
The upset-fault-observer: A concept for self-healing adaptive fault tolerance
TLDR
The upset-fault-observer (UFO), an innovative run-time self-test and recovery strategy that delivers FT on request over several function cores but saves the redundancy scalability cost by running periodic reconfigurable TMR scan-cycles, and an adaptive software organization model to manage the proposed FT strategies.

References

SHOWING 1-10 OF 14 REFERENCES
New Techniques for Improving the Performance of the Lockstep Architecture for SEEs Mitigation in FPGA Embedded Processors
The growing availability of embedded processors inside FPGAs provides unprecedented flexibility for system designers. The use of such devices for space or mission critical applications, however, is
A Fault-Tolerant Layer for Dynamically Reconfigurable Multi-processor System-on-Chip
TLDR
A modification of the standard methodology of the runtime self-reconfiguration, who facilitates the complex modular concept design, is presented in this paper.
SEU-induced persistent error propagation in FPGAs
This paper introduces a new way to characterize the dynamic single-event upset (SEU) cross section of an FPGA design in terms of its persistent and nonpersistent components. An SEU in the persistent
Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration
TLDR
A technique for ensuring reliable softcore processor implementation on SRAM-based FPGAs using triple modular redundancy (TMR) and partial reconfiguration (PR) with state synchronization and it is confirmed that a faultysoftcore processor can be recovered and synchronized with other softcore processors.
An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications
TLDR
A novel configuration scrubbing core, instantiated at the top level of the user project, is used for internal detection and correction of SEU-induced configuration errors without requiring further external radiation hardened control hardware.
Correcting single-event upsets through virtex partial configuration
This application note describes the use of partial reconfiguration in VirtexTM series FPGAs for the purpose of correcting Single Event Upsets to the configuration memory array induced by cosmic rays.
Fine-Grain SEU Mitigation for FPGAs Using Partial TMR
The mitigation of single-event upsets (SEUs) in field-programmable gate arrays (FPGAs) is an increasingly important subject as FPGAs are used in radiation environments such as space. Triple modular
Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations
An important feature in the Xilinx VirtexTM architecture is the ability to reconfigure a portion of the FPGA while the remainder of the design is still operational. Partial reconfiguration is useful
Increasing Reliability of FPGA-Based Adaptive Equalizers in the Presence of Single Event Upsets
Reliability is a major concern for electronic circuits, especially for those that operate in harsh environments. One source of problems are Single Event Upsets (SEU), which change the value of flip
RADIATION TESTING UPDATE, SEU MITIGATION, AND AVAILABILITY ANALYSIS OF THE VIRTEX FPGA FOR SPACE RECONFIGURABLE COMPUTING.
Orbital remote sensing instruments and systems can benefit from high performance, adaptable components. Field programmable SRAM-based gate arrays (FPGAs) are usually the chosen platform for real-time
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