Fault Simulation Using Partially Reconfigurable Hardware

@inproceedings{Parreira2003FaultSU,
  title={Fault Simulation Using Partially Reconfigurable Hardware},
  author={Abilio Parreira and Jo{\~a}o Paulo Teixeira and A. Pantelimon and Marcelino B. Santos and Jos{\'e} T. de Sousa},
  booktitle={FPL},
  year={2003}
}
This paper presents a fault simulation algorithm that uses efficient partial reconfiguration of FPGAs. The methodology is particularly useful for evaluation of BIST effectiveness, and for applications in which multiple fault injection is mandatory, such as safety-critical applications. A novel fault collapsing methodology is proposed, which efficiently leads to the minimal stuck-at fault list at the look-up-tables’ terminals. Fault injection is performed using local partial reconfiguration with… CONTINUE READING

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