Fault Simulation Using Partially Reconfigurable Hardware

  title={Fault Simulation Using Partially Reconfigurable Hardware},
  author={Abilio Parreira and Jo{\~a}o Paulo Teixeira and A. Pantelimon and Marcelino B. Santos and Jos{\'e} T. de Sousa},
This paper presents a fault simulation algorithm that uses efficient partial reconfiguration of FPGAs. The methodology is particularly useful for evaluation of BIST effectiveness, and for applications in which multiple fault injection is mandatory, such as safety-critical applications. A novel fault collapsing methodology is proposed, which efficiently leads to the minimal stuck-at fault list at the look-up-tables’ terminals. Fault injection is performed using local partial reconfiguration with… CONTINUE READING

From This Paper

Figures, tables, and topics from this paper.


Publications citing this paper.
Showing 1-7 of 7 extracted citations


Publications referenced by this paper.
Showing 1-10 of 19 references


S. Guccione
Levi, P.Sundararajan, “Jbits: A Java-based Interface for Reconfigurable Computing”, Proc. of the 2nd Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD), pp. 27 • 1999
View 3 Excerpts
Highly Influenced

Dynamic Fault Injection Optimization for FPGA-Based Harware Fault Simulation

M. B. Santos, J. Braga, I. M. Teixeira, J. P. Teixeira
Proc. of the Design and Diagnostics of Electronic Circuits and Systems Workshop (DDECS), pp. 370-373, April • 2002
View 2 Excerpts

Fault emulation: A new methodology for fault grading

IEEE Trans. on CAD of Integrated Circuits and Systems • 1999
View 2 Excerpts

Sequential circuit fault simulation using logic emulation

IEEE Trans. on CAD of Integrated Circuits and Systems • 1998
View 1 Excerpt

Similar Papers

Loading similar papers…