FastLanes: An FPGA accelerated GPU microarchitecture simulator

@article{Fang2013FastLanesAF,
  title={FastLanes: An FPGA accelerated GPU microarchitecture simulator},
  author={Kuan Fang and Yufei Ni and Jiayuan He and Zonghui Li and Shuai Mu and Yangdong Deng},
  journal={2013 IEEE 31st International Conference on Computer Design (ICCD)},
  year={2013},
  pages={241-248}
}
Graphic Processing Units (GPUs) have emerged as a new general purpose computing platform that attracts significant research efforts. Currently, GPU architecture research resorts to time-consuming software simulations to evaluate microarchitecture innovations. In this paper, we propose FastLanes, an FPGA based simulator for a generic GPU microarchitecture, to enable hardware-accelerated simulation. FastLanes consists of a function model and a timing model, both implemented on FPGA. The… CONTINUE READING

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