Fast triggering in high-energy physics experiments using hardware neural networks

@article{Denby2003FastTI,
  title={Fast triggering in high-energy physics experiments using hardware neural networks},
  author={Bruce Denby and Patrick Garda and B. Granado and Ch. Kiesling and Jean-Christophe Pr{\'e}votet and Andreas Wassatsch},
  journal={IEEE transactions on neural networks},
  year={2003},
  volume={14 5},
  pages={
          1010-27
        }
}
High-energy physics experiments require high-speed triggering systems capable of performing complex pattern recognition at rates of Megahertz to Gigahertz. Neural networks implemented in hardware have been the solution of choice for certain experiments. The neural triggering problem is presented here via a detailed look at the H1 level 2 trigger at the HERA accelerator, Hamburg, Germany, followed by a section on the importance of hardware preprocessing for such systems, and finally some new… 
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References

SHOWING 1-10 OF 48 REFERENCES
Hardware preprocessing for the H1-Level 2 neural network trigger upgrade
TLDR
An improved "intelligent" preprocessing has been devised to provide increased selectivity at the higher luminosity planned for the HERA upgrade, and a new preprocessing board is currently being designed at the Max Planck Institute for Physics.
Realization of a second level neural network trigger for the H1 experiment at HERA
An analog neural network processor with programmable topology
TLDR
The architecture, implementation, and applications of a special-purpose neural network processor are described and the practicality of the chip is demonstrated with an implementation of a neural network for optical character recognition.
Neural Network Adaptations to Hardware Implementations
TLDR
In this section an overview is given of the various issues that are encountered when mapping an ideal neural network model onto a compact and reliable neural network hardware implementation, like quantization, handling nonuniformities and nonideal responses, and restraining computational complexity.
Spert-II: A Vector Microprocessor System
TLDR
A prototype full custom vector microprocessor, TO, is packaged as the Spert-II (Synthetic Perceptron Testbed II) workstation accelerator system, to accelerate multiparameter neural network training for speech recognition research.
The H1 detector at HERA
DOLFIN-digit online for integration neural networks
  • A. Wassatsch, M. Haase, D. Timmermann
  • Computer Science, Mathematics
    2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353)
  • 2000
TLDR
The goal of this paper is to develop a strategy for the implementation of different network models with significant advantages over all other digital implementations by using digit online arithmetic in the field of neural network computation.
Design of high speed MOS multiplier and divider using redundant binary representation
TLDR
This work improved the algorithm and the method of implementation, and designed an advanced multiplier and divider for MOS LSI based on a new algorithm that has several excellent features such as high speed addition operations.
...
1
2
3
4
5
...