# Fast software polar decoders

@article{Giard2013FastSP, title={Fast software polar decoders}, author={Pascal Giard and Gabi Sarkis and Claude Thibeault and Warren J. Gross}, journal={2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)}, year={2013}, pages={7555-7559} }

Among error-correcting codes, polar codes are the first to provably achieve channel capacity with an explicit construction. In this work, we present software implementations of a polar decoder that leverage the capabilities of modern general-purpose processors to achieve an information throughput in excess of 200 Mbps, a throughput well suited for software-defined-radio applications. We also show that, for a similar error-correction performance, the throughput of polar decoders both surpassesâ€¦Â

## 15 Citations

### Low-Latency Software Polar Decoders

- Computer ScienceJ. Signal Process. Syst.
- 2018

It is shown how adapting the algorithm at various levels can lead to significant improvements in latency and throughput, yielding polar decoders that are suitable for high-performance software-defined radio applications on modern desktop processors and embedded-platform processors.

### Low-Latency Software Polar Decoders

- Computer ScienceJournal of Signal Processing Systems
- 2016

It is shown how adapting the algorithm at various levels can lead to significant improvements in latency and throughput, yielding polar decoders that are suitable for high-performance software-defined radio applications on modern desktop processors and embedded-platform processors.

### High-performance software implementations of SCAN decoder for polar codes

- Computer ScienceAnn. des TĂ©lĂ©communications
- 2018

This paper presents the first optimized software implementation of a SCAN decoder for Polar codes, and demonstrates that the proposed software polar decoder can exceed 600 Mb/s on a single core and reaches multi-Gb/s when using four cores simultaneously.

### Autogenerating software polar decoders

- Computer Science2014 IEEE Global Conference on Signal and Information Processing (GlobalSIP)
- 2014

This work presents a framework for generating fully-unrolled software polar decoders with branchless data flow, and discusses the memory layout of data in these decmoders and shows the optimization techniques used.

### Multi-Gb/s Software Decoding of Polar Codes

- Computer ScienceIEEE Transactions on Signal Processing
- 2015

An optimized software implementation of a Successive Cancellation (SC) decoder for polar codes that exceeds 1 Gb/s for code lengths N â‰¤ 217 on a single core and reaches multi-Gb/s throughputs when using four cores in parallel in AVX mode.

### Increasing the speed of polar list decoders

- Computer Science2014 IEEE Workshop on Signal Processing Systems (SiPS)
- 2014

Simulation results show that the proposed system is up to 16 times faster than an LDPC decoder of the same frame size, code rate, and similar error-correction performance, making it more suitable for use as a software decoding solution.

### An Efficient, Portable and Generic Library for Successive Cancellation Decoding of Polar Codes

- Computer ScienceLCPC
- 2015

The P-EDGE environment, introduced in this paper, combines a specialized skeleton generator and a building blocks library routines to provide a generic, extensible Polar code exploration workbench that enables ECC code designers to easily experiments with combinations of existing and new optimizations, while delivering performance close to state-of-art decoders.

### Low-Latency Segmented List-Pruning Software Polar List Decoder

- Computer ScienceIEEE Transactions on Vehicular Technology
- 2020

Two novel algorithms are proposed to reduce the latency of the successive cancellation list (SCL) decoding, including the segmented list-pruning (SLP) algorithm and the modified distributed sorting (MDS) algorithm, which improves the decoding performance compared to existing segmentation schemes.

### Transport Triggered Polar Decoders

- Computer Science2018 IEEE 10th International Symposium on Turbo Codes & Iterative Information Processing (ISTC)
- 2018

The first transport triggered architecture (TTA) customized for the decoding of polar codes is proposed and can be seen as a way to reduce the gap between programmable and dedicated polar decoders.

### Low-latency software successive cancellation list polar decoder using stage-located copy

- Computer Science2016 IEEE International Conference on Digital Signal Processing (DSP)
- 2016

A stage-located copy algorithm is proposed to avoid copying the same contents in candidate paths, which significantly reduces the processing latency and the resulting data processing speedup increases with code length.

## References

SHOWING 1-10 OF 18 REFERENCES

### Fast Polar Decoders: Algorithm and Implementation

- Computer ScienceIEEE Journal on Selected Areas in Communications
- 2014

This work aims to increase the throughput of polar decoding hardware by an order of magnitude relative to successive-cancellation decoders and is more than 8 times faster than the current fastest polar decoder.

### Scalable successive-cancellation hardware decoder for polar codes

- Computer Science2013 IEEE Global Conference on Signal and Information Processing
- 2013

This work presents an architecture and an implementation of a scalable hardware decoder based on the successive-cancellation algorithm, which can be designed for very long codes, with low hardware complexity, leveraging the regular structure of such codes.

### A Semi-Parallel Successive-Cancellation Decoder for Polar Codes

- Computer ScienceIEEE Transactions on Signal Processing
- 2013

The derived architecture has a very low processing complexity while the memory complexity remains similar to that of previous architectures, which allows very large polar code decoders to be implemented in hardware.

### A Scalable Successive-Cancellation Decoder for Polar Codes

- Computer ScienceIEEE Transactions on Signal Processing
- 2014

This paper presents an improved architecture for successive-cancellation decoding of polar codes, making use of a novel semi-parallel, encoder-based partial-sum computation module, and explores various optimization techniques such as a chained processing element and a variable quantization scheme.

### Increasing the Throughput of Polar Decoders

- BusinessIEEE Communications Letters
- 2013

An improved version of the simplified successive-cancellation decoding algorithm that increases decoding throughput without degrading the error-correction performance is presented.

### A two phase successive cancellation decoder architecture for polar codes

- Computer Science2013 IEEE International Symposium on Information Theory
- 2013

The results show that the proposed two-phase successive cancellation decoder architecture for polar codes has lower complexity, lower memory utilization with higher throughput, and a clock frequency that is less sensitive to code length.

### How to Construct Polar Codes

- Computer ScienceIEEE Transactions on Information Theory
- 2013

A method for efficiently constructing polar codes is presented and analyzed, proving that for any fixed Îµ > 0 and all sufficiently large code lengths n, polar codes whose rate is within Îµ of channel capacity can be constructed in time and space that are both linear in n.

### A Simplified Successive-Cancellation Decoder for Polar Codes

- Computer ScienceIEEE Communications Letters
- 2011

A modification is introduced of the successive-cancellation decoder for polar codes, in which local decoders for rate-one constituent codes are simplified. This modification reduces the decodingâ€¦

### A successive cancellation decoder ASIC for a 1024-bit polar code in 180nm CMOS

- Computer Science2012 IEEE Asian Solid State Circuits Conference (A-SSCC)
- 2012

The implemented ASIC relies on a semi-parallel architecture where processing resources are reused to achieve good hardware efficiency and a speculative decoding technique is employed to increase the throughput by 25% at the cost of very limited added complexity.

### Channel polarization: A method for constructing capacity-achieving codes

- Computer Science2008 IEEE International Symposium on Information Theory
- 2008

A method is proposed to construct code sequences that achieve the symmetric capacity I(W) of any given binary-input discrete memoryless channel (B-DMC) W, which is the highest rate achievable subject to using the input letters of the channel equiprobably.