Fast prototyping of memory models in VHDL for hardware emulation


In this paper, we present a methodology whereby the whole synthesis and prototyping cycle can be speeded up simply by extending the acceptable VHDL subset to include hitherto unsynthesisable constructs. VHDL elaboration transformations as well as some compiler optimisation techniques can be performed to ensure that the VHDL model is still acceptable by… (More)
DOI: 10.1109/IWRSP.1996.506736


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