Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications

@article{Sheng2010FastlockAD,
  title={Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications},
  author={Duo Sheng and Ching-Che Chung and Chen-Yi Lee},
  journal={IEICE Electronic Express},
  year={2010},
  volume={7},
  pages={634-639}
}
A fast-lock and portable all-digital delay-locked loop (ADDLL) with 90◦ phase shift and tunable digitally-controlled phase shifter (DCPS) for DDR controller applications are presented. The ADDLL can achieve small phase-shift error in 1.3◦ at 400 MHz and locking time of less than 13 clock cycles, making it very suitable for low-power DDR controller with… CONTINUE READING