Fast inference of Boosted Decision Trees in FPGAs for particle physics

@article{Summers2020FastIO,
  title={Fast inference of Boosted Decision Trees in FPGAs for particle physics},
  author={Sioni Summers and Giuseppe Di Guglielmo and Javier Mauricio Duarte and Philip C. Harris and Duc A. Hoang and Sergo Jindariani and Edward Kreinar and Vladimir Loncar and Jennifer Ngadiuba and Maurizio Pierini and Dylan S. Rankin and Nhan Viet Tran and Zhenbin Wu},
  journal={Journal of Instrumentation},
  year={2020},
  volume={15},
  pages={P05026 - P05026}
}
We describe the implementation of Boosted Decision Trees in the hls4ml library, which allows the translation of a trained model into FPGA firmware through an automated conversion process. Thanks to its fully on-chip implementation, hls4ml performs inference of Boosted Decision Tree models with extremely low latency. With a typical latency less than 100 ns, this solution is suitable for FPGA-based real-time processing, such as in the Level-1 Trigger system of a collider experiment. These… 
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