Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration

Abstract

Simulation is a bottleneck in the design flow of on-chip multiprocessors. This paper addresses that problem by reducing the simulation time of complex on-chip interconnects through transaction-level modelling (TLM). A particular on-chip interconnect architecture was chosen, namely a wormhole network-on-chip with priority preemptive virtual channel arbitration, because its mechanisms can be modelled at transaction level in such a way that accurate figures for communication latency can be obtained with less simulation time than a cycle-accurate model. The proposed model produced latency figures with more than 90% accuracy and simulated more than 1000 times faster than a cycle-accurate model.

DOI: 10.1109/DATE.2011.5763179
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@article{Indrusiak2011FastAA, title={Fast and accurate transaction-level model of a wormhole network-on-chip with priority preemptive virtual channel arbitration}, author={Leandro Soares Indrusiak and Osmar Marchi dos Santos}, journal={2011 Design, Automation & Test in Europe}, year={2011}, pages={1-6} }