Fast and accurate activity evaluation in multipliers

  • Arnaud Tisserand
  • Published 2008 in
    2008 42nd Asilomar Conference on Signals, Systems…

Abstract

This article reports the first results on fast and accurate power evaluation in arithmetic operators. The proposed method uses two steps: 1) accurate useful activity evaluation, 2) fast glitching activity estimation. The first step is based on circuit emulation using FPGA. Activity counters are inserted into the low-level description of the evaluated… (More)

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