Fast STA prediction-based gate-level timing simulation

Abstract

Traditional dynamic simulation with standard delay format (SDF) back-annotation cannot be reliably performed on large designs. The large size of SDF files makes the event-driven timing simulation extremely slow as it has to process an excessive number of events. In order to accelerate gate-level timing simulation we propose an automated fast prediction-based gatelevel timing simulation that combines static timing analysis (STA) at the block level with dynamic timing simulation at the I/O interfaces. We demonstrate that the proposed timing simulation can be done earlier in the design cycle in parallel with synthesis.

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Cite this paper

@article{Ahmad2014FastSP, title={Fast STA prediction-based gate-level timing simulation}, author={Tariq B. Ahmad and Maciej J. Ciesielski}, journal={2014 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, year={2014}, pages={1-6} }