# Fast Multiplication Without Carry-Propagate Addition

@article{Ercegovac1990FastMW, title={Fast Multiplication Without Carry-Propagate Addition}, author={Milos D. Ercegovac and Tom{\'a}s Lang}, journal={IEEE Trans. Computers}, year={1990}, volume={39}, pages={1385-1390} }

Conventional schemes for fast multiplication accumulate the partial products in redundant form (carry-save or signed-digit) and convert the result to conventional representation in the last step. This step requires a carry-propagate adder which is comparatively slow and occupies a significant area of the chip in a VLSI implementation. A report is presented on a multiplication scheme (left-to-right, carry-free, LRCF) that does not require this carry-propagate step. The LRCF scheme performs the…

## 95 Citations

### n /spl times/ n carry-save multipliers without final addition

- Computer ScienceProceedings of IEEE 11th Symposium on Computer Arithmetic
- 1993

The resulting implementation, when a radix-2 adder array is used, produces a result on 2n bits with a delay comparable to that of the multiplier proposed by M.D. Ercegovac and T. Lang (1990).

### On-the-Fly Rounding

- Computer ScienceIEEE Trans. Computers
- 1992

Three ways to modify this conversion process so that the result is rounded are described, which can be done on-the-fly as the digits are produced, without the use of a carry-propagate adder.

### Carry-Save Multiplication Schemes without Final Addition

- Computer ScienceIEEE Trans. Computers
- 1996

This paper presents n/spl times/n multiplication schemes where the full 2n-bit result is produced, unlike similar multiplication schemes presented in the literature.

### Module to Perform Multiplication, Division, and Square Root in Systolic Arrays for Matrix Computations

- Computer ScienceJ. Parallel Distributed Comput.
- 1991

### Left-to-right carry-free scheme for computing ab+cd

- Computer ScienceConference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154)
- 2000

A radix-4 scheme is proposed for computing the sum of products s=ab+cd using left-to-right multipliers and on-the-fly conversion. The final result is obtained without the extra delay of a…

### Implementation of module combining multiplication, division, and square root

- Computer ScienceIEEE International Symposium on Circuits and Systems,
- 1989

The implementation of a module that performs radix-2 multiplication, division, and square root is presented, which incorporates on-the-fly conversion and routing of the result.

### Left-to-right squarer with overlapped LS and MS parts

- Computer ScienceThe Thrity-Seventh Asilomar Conference on Signals, Systems & Computers, 2003
- 2003

A radix-4 scheme is proposed for computing the square s=x/sup 2/ using left-to-right multiplication algorithm and on-the-fly conversion and the critical path is kept small by the use of redundant arithmetic.

### Design of Fast Efficient Radix-16 Sequential Multiplier

- Computer ScienceVOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE
- 2019

The proposed design of radix-16 sequential multiplier is efficient over previous designs and comparison depicts ADP and PDP of existing method are 11.22% and 8.45% less than proposed method.

### Fast Arithmetic Using Signed Digit Numbers and Ternary Logic

- Computer Science
- 2009

Redundant Binary Signed Digit Number System may not be convenient for manual computations but may be useful in designing high‐speed arithmetic machines and use of parallel implementation for architectures is discussed.

### VLSI implementation of a 200-MHz 16/spl times/16 left-to-right carry-free multiplier in 0.35 /spl mu/m CMOS technology for next-generation DSPs

- Computer ScienceProceedings of CICC 97 - Custom Integrated Circuits Conference
- 1997

The VLSI implementation of a 16/spl times/16 left-to-right carry-free multiplier is described and two conversion schemes for converting the most significant half of the partial products from carry-save to binary form are described.

## References

SHOWING 1-10 OF 19 REFERENCES

### Signed-Digit Numbe Representations for Fast Parallel Arithmetic

- Mathematics, Computer ScienceIRE Trans. Electron. Comput.
- 1961

Sign-digit representations limit carry-propagation to one position to the left during the operations of addition and subtraction in digital computers and arithmetic operations with signed-digit numbers: addition, subtraction, multiplication, division and roundoff are discussed.

### A CMOS floating point multiplier

- EngineeringIEEE Journal of Solid-State Circuits
- 1984

A 32-bit CMOS floating-point multiplier is described, designed for compatibility with 16-bit microcomputer systems, and fabricated in 2-/spl mu/m n-well CMOS technology.

### On-the-Fly Conversion of Redundant into Conventional Representations

- Computer ScienceIEEE Transactions on Computers
- 1987

An algorithm to convert redundant number representations into conventional representations is presented, which is applicable in arithmetic algorithms such as nonrestoring division, square root, and on-line operations in which redundantly represented results are generated in a digit-by-digit manner.

### 16-bit CMOS/SOS multiplier-accumulator

- Computer Science
- 1982

A high speed and low power 16-bit parallel multiplier with an accumulator on a chip, which performs 16-bit*16-bit multiplication and accumulation in 60 ns with 65 mw, is described. The LSI uses a…

### A high-speed multiplier using a redundant binary adder tree

- Computer Science
- 1987

A 16-bit/spl times/16-bit multiplier for 2 two's-complement binary numbers based on a new algorithm is described, characterized by use of a binary tree of redundant binary adders.

### Design of high speed MOS multiplier and divider using redundant binary representation

- Computer Science1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)
- 1987

This work improved the algorithm and the method of implementation, and designed an advanced multiplier and divider for MOS LSI based on a new algorithm that has several excellent features such as high speed addition operations.

### A systematic approach to the design of structures for arithmetic

- Computer Science1981 IEEE 5th Symposium on Computer Arithmetic (ARITH)
- 1981

A design tool for the decomposition of binary digital structures for addition and subtraction has been developed. A simplified theory reduces a complex structure to a collection of basic structures…

### An implementation guide to a proposed standard for floating-point arithmetic

- Computer Science
- 1980

This standard is a product of the Floating-Point Working Group of the Microprocessor Standards Subcommittee of the Standards Committee of the IEEE Computer Society. This work was sponsored by the…

### On the C-Testability of Generalized Counters

- Computer Science, MathematicsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- 1987

It is shown that counter circuits can always be designed to be testable with either eight or ten tests, irrespective of the input size.

### Special Feature an Implementation Guide to a Proposed Standard for Floating-Point Arithmetic

- Computer ScienceComputer
- 1980

This guide to an IEEE draft standard provides practical algorithms for floating-point arithmetic operations and suggests the hardware/software mix for handling exceptions.