Fast Estimation of Timing Yield Bounds for Process Variations


With aggressive scaling down of feature sizes in VLSI fabrication, process variation has become a critical issue in designs. We show that two necessary conditions for the ldquomaxrdquo operation are actually not satisfied in the moment matching based statistical timing analysis approaches. We propose two correlation-aware block-based statistical timing… (More)
DOI: 10.1109/TVLSI.2007.915398


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