Corpus ID: 18046362

Fast Charge Pump Phase Locked Loop with a BBFC: A Numerical Confirmation

  title={Fast Charge Pump Phase Locked Loop with a BBFC: A Numerical Confirmation},
  author={V. Sadeghi and H. Naimi},
  • V. Sadeghi, H. Naimi
  • Published 2012
  • Computer Science
  • Speeding up a synthesizer's locking process can be considered as speeding up the charge pump PLL. Several methods have been introduced to increase the speed of the locking process. One way to achieve fast locking is to use a bang- bang frequency comparator (BBFC) in the feed-trough path to achieve a faster locking process. In this paper, we present a differential equation for this fast CPPLL which shows how the BBFC can decrease the settling time in a charge pump PLL. Simulations in MATLAB are… CONTINUE READING

    Figures, Tables, and Topics from this paper


    Fast locking and high accurate current matching phase-locked loop
    • Silin Liu, Y. Shi
    • Engineering, Computer Science
    • APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
    • 2008
    • 9
    • PDF
    A fast synthesizer using a bang-bang frequency comparator and locking status indicator
    • V. Sadeghi, H. Naimi
    • Engineering, Computer Science
    • Proceedings of the 2011 International Conference on Electrical Engineering and Informatics
    • 2011
    • 7
    Analysis of a PLL based frequency synthesizer using switched loop bandwidth for Mobile WiMAX
    • 15
    • PDF
    Design of Analog CMOS Integrated Circuits
    • 2,537
    • PDF