• Corpus ID: 18561204

Fast Charge Pump Circuit for PLL using 50nm CMOS Technology

@inproceedings{Singh2013FastCP,
  title={Fast Charge Pump Circuit for PLL using 50nm CMOS Technology},
  author={Yogendra Pratap Singh and M. Mohan},
  year={2013}
}
PLL being a mixed signal circuit involves design challenge at high frequency. This work analyses the design of a mixed signal phase locked loop for faster phase and frequency locking. The performance of charge pumps depends heavily on the ability to efficiently generate high voltages on-chip while meeting stringent power and area requirements. The paper presents a High Speed CMOS charge pump circuit for PLL applications using 50nm CMOS technology that operates at 1V. The proposed circuit has… 

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