Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates

@article{Knezevic2012FairAC,
  title={Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates},
  author={Miroslav Knezevic and Kazuyuki Kobayashi and Jun Ikegami and Shin'ichiro Matsuo and Akashi Satoh and {\"U}nal Koçabas and Junfeng Fan and Toshihiro Katashita and Takeshi Sugawara and Kazuo Sakiyama and Ingrid Verbauwhede and Kazuo Ohta and Naofumi Homma and Takafumi Aoki},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2012},
  volume={20},
  pages={827-840}
}
The first contribution of our paper is that we propose a platform, a design strategy, and evaluation criteria for a fair and consistent hardware evaluation of the second-round SHA-3 candidates. Using a SASEBO-GII field-programmable gate array (FPGA) board as a common platform, combined with well defined hardware and software interfaces, we compare all 256-bit version candidates with respect to area, throughput, latency, power, and energy consumption. Our approach defines a standard testing… CONTINUE READING
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