Failure analyses of 3D Sip (system-in-package) and WLP (wafer-level package) by finite element methods

@article{Lau2009FailureAO,
  title={Failure analyses of 3D Sip (system-in-package) and WLP (wafer-level package) by finite element methods},
  author={John H. Lau and Xiaowu Zheng and C. S. Selvanayagam},
  journal={2009 16th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits},
  year={2009},
  pages={108-116}
}
In this study, three examples of failure analyses of electronic packaging by using the finite element method are presented. These are: (1) the failures (delaminations) near the interface between the filled copper and the silicon and between the copper and the silicon dioxide dielectric of the TSV of a 3D system-in-package (SiP) due to the local thermal expansion mismatch between the silicon and the filled copper; (2) the failures of the microbumps between the fine-pitch IC chip and the TSV… CONTINUE READING