Fabrication of silicon nanowires

Abstract

Pentagon-shaped silicon wires with linewidth around 300 nm are successfully fabricated by using the Si/SiGe epitaxy technique, reactive ion etching, and subsequent selective chemical etching. The nanowires are oxidized in wet O2 at 750 ◦C and 850 ◦C. The oxide and interface morphology are characterized by cross-sectional scanning electron microscope images. It is found that the oxidized nanowire following oxidation at 750 ◦C still keeps its pentagon shape even if it has been oxidized for 19 h. However, the oxidized samples at 850 ◦C become circular in shape. The oxidation-temperature dependence of the sample shapes is discussed. Our results should be useful in generating silicon nanowires coated with SiO2 in microelectronic technology with careful selection of the SiO2 growth temperatures. PACS: 85.42; 81.15; 81.60 Field-effect devices having SiO2-coated silicon nanowires acting as trenches have recently received great attention, since new physical phenomena with applications in future verylarge-scale integration (VLSI) devices are expected [1, 2]. Transport properties in these devices depend on the size and shape of the silicon wires. As a result, study of the thermal oxidation of silicon nanowires of various sizes and shapes, as a key process in fabricating SiO2-coated silicon nanowire field-effect devices, is very important. Up to now, much interest has been focused on the oxidation of silicon cylinders. Early work was done by Kao et al. with silicon cylinder diameters larger than 1 μm [3]. Oxidation of silicon cylindrical structures has also been studied by J.L. Liu et al. with silicon wire linewidths ranging from 40 nm to 250 nm [4], and by H.I. Liu et al. with silicon columns of dimensions below 10 nm [5]. In addition, other authors have studied oxidation of triangle-shaped silicon nanowires [6, 7]. All these works have provided a controllable way of defining the size and shape of silicon nanowires, which is very useful in fabricating expected silicon nanowire field-effect devices. At the present stage, there is still an urgent need to obtain oxidation results for silicon nanowires of other shapes. It is well known that SiGe/Si heteroepitaxial film is very useful in fabricating various silicon wires and related devices because of its excellent properties, such as high-quality epitaxial growth, selective etching, and thermal oxidation. Recently, formation of silicon quantum wires with the physical boundaries of SiO2 based on a SiGe heterostructure have been reported [4]. Here, we describe the fabrication and oxidation of pentagon-shaped Si nanowires. This process was done by first growing a high-quality Si/Si1−xGex/Si heteroepitaxial film on a Si substrate by very low pressure chemical vapor deposition (VLP/CVD), followed by lithography and reactive ion etching to form trench structures. Subsequently, the selective chemical wet etching with a solution of HNO3:CH3COOH:diluted HF was used to remove the Si1−xGex layer and form pentagon-shaped silicon wires. Finally, thermal oxidation in wet O2 was carried out and the oxide morphology was characterized by scanning electron microscopy (SEM). The thermal oxidation of pentagonshaped wires will be discussed. Figure 1a is a schematic of a pentagon-shaped silicon wire structure. The structure was generated as follows. The silicon substrate was a 〈100〉-oriented p-type silicon wafer with a resistivity of 25–50 Ω cm. First, a Si/SiGe/Si layer was deposited on the substrate by VLP/CVD with SiH4 and GeH4 as the gaseous sources. It started with a Si buffer layer of 100 nm, followed by a graded Si1−xGex layer of 200 nm with the Ge content x decreasing linearly from 0.2 to 0. High-quality superficial silicon layer was deposited on top of these strain adjusting layers. Then, masks with line-and-space patterns parallel to the 〈110〉 direction were lithographically defined on the Si/Si1−xGex/Si epitaxial film. The trench structures were generated by reactive ion etching using SF6 gas. Next, the substrate was dipped into HNO3:CH3COOH:diluted HF in order to create the silicon nanowires. Note that the selective chemical etchant HNO3:CH3COOH:diluted HF was very effective in reducing SiGe nanostructures, and a higher etch rate is obtained by increasing the Ge content in the Si1−xGex layer [8]. As a result, for the present graded Si1−xGex layer, the etch rate at the bottom layer of the Si1−xGex is higher than that at the upper

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@inproceedings{Liu1998FabricationOS, title={Fabrication of silicon nanowires}, author={Jingbo Liu and Y. Lu and Y. Shi and S. L. Gu and Ruisong Jiang and Fuqiang Wang and Y. D. Zheng}, year={1998} }