• Corpus ID: 40873390

FPGA with Improved Routability and Robustness in 130nm CMOS with Open-Source CAD Targetability

@article{Yu2017FPGAWI,
  title={FPGA with Improved Routability and Robustness in 130nm CMOS with Open-Source CAD Targetability},
  author={Guanshun Yu and Tom Y. Cheng and Blayne Kettlewell and Harrison Liew and Mingoo Seok and Peter R. Kinget},
  journal={ArXiv},
  year={2017},
  volume={abs/1712.03411}
}
This paper outlines an FPGA VLSI design methodology that was used to realize a fully functioning FPGA chip in 130nm CMOS with improved routability and memory robustness. The architectural design space exploration and synthesis capability were enabled by the Verilog-to-Routing CAD tool. The capabilities of this tool were extended to enable bitstream generation and deployment. To validate the architecture and bitstream implementation, a Chisel (Constructing Hardware in the Embedded Scala Language… 

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