FPGA implementation of delay optimized single precision floating point multiplier

@article{Paldurai2015FPGAIO,
  title={FPGA implementation of delay optimized single precision floating point multiplier},
  author={K. Paldurai and K. Hariharan},
  journal={2015 International Conference on Advanced Computing and Communication Systems},
  year={2015},
  pages={1-5}
}
  • K. Paldurai, K. Hariharan
  • Published 2015
  • Computer Science
  • 2015 International Conference on Advanced Computing and Communication Systems
Multiplication of floating point numbers found extensive use in DSP applications involving huge range. The critical part in floating point multiplication is the multiplication of mantissas which uses 24*24 bit integer multiplier for single precision floating point numbers. The speed of the system can be enhanced by improving the speed of multiplication. In this paper a 24 bit Vedic multiplier has been proposed using 3*3 Vedic multiplier as its basic block. This paper proposes a IEEE-754 single… Expand
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