FPGA implementation of a new parallel routing algorithm


This paper presents a new parallel processing wire routing algorithm, which finds a quasi-minimum Steiner tree for multi-point connections in a VLSI chip or a PCB. A VHDL code is written to implement the algorithm on a prototype 4times4 and 8times8 single layer grid. Two methods are proposed for the design of processing element. The algorithm has been… (More)


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