FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability

@article{Kalokerinos2009FPGAIO,
  title={FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability},
  author={George Kalokerinos and Vassilis Papaefstathiou and George Nikiforos and Stamatis G. Kavadias and Manolis Katevenis and Dionisios N. Pnevmatikatos and Xiaojun Yang},
  journal={2009 International Symposium on Systems, Architectures, Modeling, and Simulation},
  year={2009},
  pages={149-156}
}
We report on the hardware implementation of a local memory system for individual processors inside future chip multiprocessors (CMP). It intends to support both implicit communication, via caches, and explicit communication, via directly accessible local (“scratchpad”) memories and remote DMA (RDMA). We provide run-time configurability of the SRAM blocks near each processor, so that part of them operates as 2nd level (local) cache, while the rest operates as scratchpad. We also strive to merge… CONTINUE READING
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