FPGA implementation of a clockless stochastic LDPC decoder

Abstract

This paper demonstrates a clockless stochastic low-density parity-check (LDPC) decoder implemented on a Field-Programmable Gate Array (FPGA). Stochastic computing reduces the wiring complexity necessary for decoding by replacing operations such as multiplication and division with simple logic gates and serial processing. Clockless decoding increases the… (More)
DOI: 10.1109/SiPS.2014.6986088

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Cite this paper

@article{Ceroici2014FPGAIO, title={FPGA implementation of a clockless stochastic LDPC decoder}, author={Chris Ceroici and Vincent C. Gaudet}, journal={2014 IEEE Workshop on Signal Processing Systems (SiPS)}, year={2014}, pages={1-5} }