FPGA implementation and verification of LDPC encoder with weight (3, 6) approximate lower triangular matrix

@article{Chen2012FPGAIA,
  title={FPGA implementation and verification of LDPC encoder with weight (3, 6) approximate lower triangular matrix},
  author={Yi Hua Chen and Meilin Su and Jheng Shyuan He},
  journal={Proceedings of 2012 2nd International Conference on Computer Science and Network Technology},
  year={2012},
  pages={531-534}
}
Compared with general linear block code encoding, LDPC encoding with lower triangular check matrix and approximate lower triangular check matrix carry out encoding directly by parity check matrix H. This study used the weight (3, 6) approximate lower triangular regular parity check matrix to implement the LDPC encoding on the 5641R FPGA of the Software Define Radio system developed by National Instruments (NI) [1]. This study provided a detailed introduction to the encoding mechanism of the… CONTINUE READING

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