FPGA design of a coordinate descent data detector for large-scale MU-MIMO

Abstract

We propose a new, low-complexity data-detection algorithm and a corresponding high-throughput FPGA design for 3GPP LTEbased large-scale (or massive) multi-user (MU) multiple-input multipleoutput (MIMO) wireless communication systems. Our algorithm performs approximate minimum mean-square error (MMSE) data detection using coordinate descent (CD), which enables near-MMSE performance at low computational complexity, even for systems with hundreds of antennas at the base station (BS). We design a high-throughput VLSI architecture for 3GPP LTE wideband systems with a deep and interleaved pipeline, which can be parametrized at design time to support various antenna configurations. Our CD-based data detector achieves 379 Mb/s throughout, while using 24 k LUTs and 771 DSP units on a Xilinx Virtex-7 FPGA for a 128 BS antenna, 8 user large-scale MU-MIMO system.

DOI: 10.1109/ISCAS.2016.7538942

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Cite this paper

@inproceedings{Wu2016FPGADO, title={FPGA design of a coordinate descent data detector for large-scale MU-MIMO}, author={Michael Wu and Chris Dick and Joseph R. Cavallaro and Christoph Studer}, booktitle={ISCAS}, year={2016} }