An Efficient FPGA IP Core for Automatic Modulation Classification
Histogram equalization method is implemented by Field Programmable Gate Arrays (FPGA) and digital signal processors (DSP) together on thermal cameras. In this paper, we discussed work load of different histogram equalization implementations on FPGA's and DSP's, and their output video quality on current systems. In these implementation methods histogram transformation function is described by 2, 16 or 256 pieces. DSP work load is totally released on 256 piece method. The number of configurable logic blocks used on FPGA is decreased without any loss on speed. By implementing 256 pieces method the complexity of the method is decreased and an increase in the quality of the output images obtained. The results are presented on scanning array thermal cameras.