Multi-parallel Architecture for MD5 Implementations on FPGA with Gigabit-level Throughput
Data integrity assurance and data origin authentication are essential security services in financial transactions, electronic commerce, electronic mail, software distribution, data storage and so on. Nowadays, consumer electronics has been shifted toward Internet or intelligent appliances (IA) with network capability to exchange information through Internet. Therefore, a hardware based security mechanism is essential to be combined into the IA so that security and performance can be both preserved. In the Internet protocol security (IPSec) mechanism, the authentication header (AH) is an important portion. The two authentication algorithms specified for AH are MD5 and SHA-1 which have been implemented and evaluated in FPGA. With the proposed enhanced (register usage and concurrent statement) operation core design, a 6% improvement for slice utilization plus 24% more throughput for MD5 are obtained comparing to the previous one.