FPGA and ASIC square root designs for high performance and power efficiency

@article{Suresh2013FPGAAA,
  title={FPGA and ASIC square root designs for high performance and power efficiency},
  author={Shashank Suresh and Spiridon F. Beldianu and Sotirios G. Ziavras},
  journal={2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors},
  year={2013},
  pages={269-272}
}
Floating-point square root is a fundamental operation in signal processing and various HPC applications. Since this is an expensive operation in resource and energy consumption, its efficient implementation should be of priority in future multicores that will face dark silicon issues. This paper presents a low-cost, low-power consumption design to calculate the square root using the IEEE754 single-precision floating-point format. Two versions of the design are investigated with and without… CONTINUE READING

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