FPGA Montgomery multiplier architectures - a comparison

  title={FPGA Montgomery multiplier architectures - a comparison},
  author={Ciaran McIvor and M{\'a}ire O'Neill and John V. McCanny},
  journal={12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines},
  • C. McIvor, M. O'Neill, J. McCanny
  • Published 20 April 2004
  • Computer Science
  • 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Novel FPGA architectures for the SOS, CIOS and FIOS Montgomery multiplication algorithms are presented. The 18/spl times/18-bit multipliers and fast carry look-ahead logic embedded within the Xilinx Virtex2 Pro family of FPGAs are used to perform the ordinary multiplications and additions required by these algorithms. A detailed analysis is given, highlighting the advantages and weaknesses of each of these architectures when implemented in hardware. This shows that the CIOS multiplier… 

Figures and Tables from this paper

Low Power Montgomery Modular Multiplication on Reconfigurable Systems
An area-optimized FPGA architecture of the Montgomery modular multiplication algorithm on a low power reconfigurable IGLOO © 2 FPGa of Microsemi © is presented.
An Efficient Reconfigurable SOS Montgomery Multiplier in GF (P) usign FPGA DSP Slices
This paper focuses on implementation of fully pipelined SOS based Montgomery Multiplication algorithm in Virtex-5 FPGA using DSP slices to achieve best area-speed trade off and results and comparison with other Multipliers show that the Multiplier is comparable to known Montgomery Multipler in terms of area- speed trade off.
Area-optimized montgomery multiplication on IGLOO 2 FPGAs
This paper presents the first area-optimized Montgomery modular multiplication module on low-power reconfigurable IGLOO® 2 FPGAs, from Microsemi, which is the first fundamental step towards area-efficient public-key cryptography on themicrosemi IGLoo® 2FPGAs.
Generation of Finely-Pipelined GF(PP) Multipliers for Flexible Curve Based Cryptography on FPGAs
A tool, distributed as open source, for generating VHDL codes with various parameters: width of operands, number of logical multipliers per physical one, speed or area optimization, possible use of BRAMs, target FPGA.
How to Maximize the Potential of FPGA-Based DSPs for Modular Exponentiation
A modular exponentiation processing method and circuit architecture that can exhibit the maximum performance of FPGA resources and can perform fast operations using small-scale resources is described.
Power Analysis of a Montgomery Modular Multiplier for Cryptosystems
The main contribution of this paper is to implement modular multiplier using Montgomery algorithm for RSA encryption and decryption using Ripple Carry Adders, Carry Look ahead Adder and Carry Save Adders to perform the large word length Addition's required by this algorithm.
Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication
  • M. O'Neill, C. McIvor, J. McCanny
  • Computer Science, Mathematics
    Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)
  • 2004
A generic coarsely integrated operand scanning (CIOS) architecture that provides high speed Montgomery modular multiplication is presented, and to the authors' knowledge this is the fastest Montgomery multiplication architecture reported in the literature.
Parametric, Secure and Compact Implementation of RSA on FPGA
We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The design utilizes dedicated
Uso eficiente de aritmética redundante en FPGAs
In this work, it is demonstrated that carry-save arithmetic can be efficiently used in FPGA, obtaining an important speed improvement with a reasonable area cost.
How to Maximize the Potential of FPGA Resources for Modular Exponentiation
A circuit architecture that can handle multiple data lengths using the same circuits and improve the Montgomery multiplication algorithm in order to maximize the performance of the multiplication unit in FPGA.


Analyzing and comparing Montgomery multiplication algorithms
The operations involved in computing the Montgomery product are studied, several high-speed, space-efficient algorithms for computing MonPro(a, b), and their time and space requirements are described.
Modular multiplication without trial division
A method for multiplying two integers modulo N while avoiding division by N, a representation of residue classes so as to speed modular multiplication without affecting the modular addition and subtraction algorithms.
A method for obtaining digital signatures and public-key cryptosystems
An encryption method is presented with the novel property that publicly revealing an encryption key does not thereby reveal the corresponding decryption key, soriers or other secure means are not needed to transmit keys.
Elliptic curve cryptosystems
The question of primitive points on an elliptic curve modulo p is discussed, and a theorem on nonsmoothness of the order of the cyclic subgroup generated by a global point is given.
Xilinx Virtex2 Pro Data Sheets
  • Xilinx Virtex2 Pro Data Sheets
Altera Corporation: http://www.altera.com, " Stratix FPGA Literature
  • Altera Corporation: http://www.altera.com, " Stratix FPGA Literature
Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
  • Proceedings of the 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines