FPGA Montgomery multiplier architectures - a comparison

@article{McIvor2004FPGAMM,
  title={FPGA Montgomery multiplier architectures - a comparison},
  author={Ciaran McIvor and M{\'a}ire O'Neill and John V. McCanny},
  journal={12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines},
  year={2004},
  pages={279-282}
}
  • C. McIvor, M. O'Neill, J. McCanny
  • Published 20 April 2004
  • Computer Science
  • 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Novel FPGA architectures for the SOS, CIOS and FIOS Montgomery multiplication algorithms are presented. The 18/spl times/18-bit multipliers and fast carry look-ahead logic embedded within the Xilinx Virtex2 Pro family of FPGAs are used to perform the ordinary multiplications and additions required by these algorithms. A detailed analysis is given, highlighting the advantages and weaknesses of each of these architectures when implemented in hardware. This shows that the CIOS multiplier… 

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    Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)
  • 2004
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