# FPGA Montgomery multiplier architectures - a comparison

@article{McIvor2004FPGAMM, title={FPGA Montgomery multiplier architectures - a comparison}, author={Ciaran McIvor and M{\'a}ire O'Neill and John V. McCanny}, journal={12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines}, year={2004}, pages={279-282} }

Novel FPGA architectures for the SOS, CIOS and FIOS Montgomery multiplication algorithms are presented. The 18/spl times/18-bit multipliers and fast carry look-ahead logic embedded within the Xilinx Virtex2 Pro family of FPGAs are used to perform the ordinary multiplications and additions required by these algorithms. A detailed analysis is given, highlighting the advantages and weaknesses of each of these architectures when implemented in hardware. This shows that the CIOS multiplier…

## 41 Citations

Low Power Montgomery Modular Multiplication on Reconfigurable Systems

- Computer Science, MathematicsIACR Cryptol. ePrint Arch.
- 2016

An area-optimized FPGA architecture of the Montgomery modular multiplication algorithm on a low power reconfigurable IGLOO © 2 FPGa of Microsemi © is presented.

An Efficient Reconfigurable SOS Montgomery Multiplier in GF (P) usign FPGA DSP Slices

- Computer Science, MathematicsSECRYPT
- 2008

This paper focuses on implementation of fully pipelined SOS based Montgomery Multiplication algorithm in Virtex-5 FPGA using DSP slices to achieve best area-speed trade off and results and comparison with other Multipliers show that the Multiplier is comparable to known Montgomery Multipler in terms of area- speed trade off.

Area-optimized montgomery multiplication on IGLOO 2 FPGAs

- Computer Science, Mathematics2017 27th International Conference on Field Programmable Logic and Applications (FPL)
- 2017

This paper presents the first area-optimized Montgomery modular multiplication module on low-power reconfigurable IGLOO® 2 FPGAs, from Microsemi, which is the first fundamental step towards area-efficient public-key cryptography on themicrosemi IGLoo® 2FPGAs.

Generation of Finely-Pipelined GF(PP) Multipliers for Flexible Curve Based Cryptography on FPGAs

- Computer Science, MathematicsIEEE Trans. Computers
- 2019

A tool, distributed as open source, for generating VHDL codes with various parameters: width of operands, number of logical multipliers per physical one, speed or area optimization, possible use of BRAMs, target FPGA.

How to Maximize the Potential of FPGA-Based DSPs for Modular Exponentiation

- Computer Science, MathematicsIEICE Trans. Fundam. Electron. Commun. Comput. Sci.
- 2011

A modular exponentiation processing method and circuit architecture that can exhibit the maximum performance of FPGA resources and can perform fast operations using small-scale resources is described.

Power Analysis of a Montgomery Modular Multiplier for Cryptosystems

- Computer Science2013 International Conference on Machine Intelligence and Research Advancement
- 2013

The main contribution of this paper is to implement modular multiplier using Montgomery algorithm for RSA encryption and decryption using Ripple Carry Adders, Carry Look ahead Adder and Carry Save Adders to perform the large word length Addition's required by this algorithm.

Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication

- Computer Science, MathematicsProceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)
- 2004

A generic coarsely integrated operand scanning (CIOS) architecture that provides high speed Montgomery modular multiplication is presented, and to the authors' knowledge this is the fastest Montgomery multiplication architecture reported in the literature.

Parametric, Secure and Compact Implementation of RSA on FPGA

- Computer Science, Mathematics2008 International Conference on Reconfigurable Computing and FPGAs
- 2008

We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The design utilizes dedicated…

Uso eficiente de aritmética redundante en FPGAs

- Computer Science
- 2013

In this work, it is demonstrated that carry-save arithmetic can be efficiently used in FPGA, obtaining an important speed improvement with a reasonable area cost.

How to Maximize the Potential of FPGA Resources for Modular Exponentiation

- Computer ScienceCHES
- 2007

A circuit architecture that can handle multiple data lengths using the same circuits and improve the Montgomery multiplication algorithm in order to maximize the performance of the multiplication unit in FPGA.

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