# FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p)

@article{McIvor2004FPGAMM, title={FPGA Montgomery modular multiplication architectures suitable for ECCs over GF(p)}, author={Ciaran McIvor and M{\'a}ire O'Neill and John V. McCanny}, journal={2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)}, year={2004}, volume={3}, pages={III-509} }

New FPGA architectures for the ordinary Montgomery multiplication algorithm and the FIOS modular multiplication algorithm are presented. The embedded 18 /spl times/ 18-bit multipliers and fast carry look-ahead logic located on the Xilinx Virtex2 Pro family of FPGAs are used to perform the ordinary multiplications and additions/subtractions required by these two algorithms. The architectures are developed for use in elliptic curve cryptosystems over GF(p), which require modular field…

## 17 Citations

FPGA-based Design of a Large Moduli Multiplier for Public-Key Cryptographic Systems

- Computer Science, Mathematics2006 International Conference on Computer Design
- 2006

A modular multiplier based on the ordinary Montgomery's multiplication algorithm and a new array multiplication scheme to perform the multiplication is presented and it is shown that the technique has better performance when compared with other schemes.

Generation of Finely-Pipelined GF(PP) Multipliers for Flexible Curve Based Cryptography on FPGAs

- Computer Science, MathematicsIEEE Trans. Computers
- 2019

A tool, distributed as open source, for generating VHDL codes with various parameters: width of operands, number of logical multipliers per physical one, speed or area optimization, possible use of BRAMs, target FPGA.

An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n)

- Computer Science, Mathematics9th EUROMICRO Conference on Digital System Design (DSD'06)
- 2006

This appears to be the only reconfigurable architecture for Montgomery multiplication over Galois prime field GF(n) that employs carry-save addition and high order of flexibility, which allows easy reconfigurability for any operand length and low hardware complexity.

A Large Scale Adaptable Multiplier for Cryptographic Applications

- Computer Science, MathematicsFirst NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)
- 2006

The objective of this work is to design large adaptable bit-length multipliers that can be employed in cryptographic systems and to suggest a novel partition of the multiplier into folded pipeline stages such that each stage can be instantiated by reconfiguration from its preceding stage during the multiplication operation.

Embedded Reconfigurable Solutions for Cryptography

- Computer Science, Mathematics
- 2008

Improvements in the CryptoRA architecture and result of a hardwaresoftware co- design on MicroBlaze embedded system for computing public-key cryptosystem algorithm can further improve the performance of the co-design solution.

Hardware implementation of elliptic curve Diffie-Hellman key agreement scheme in GF(p)

- Computer Science, Mathematics
- 2008

This thesis examines various scalable implementations of elliptic curve scalar multiplication employing multiplicative inverse or field division in GF(p) focussing mainly on modular divison architectures and presents a new architecture for modular division based on the variant of Extended Binary GCD algorithm.

Design of a Reconfigurable Processor for Elliptic Curve Cryptography over NIST Prime Fields

- Computer Science, Mathematics
- 2006

The proposed processor can be reconfigured to work with any of the five prime fields recommended by NIST (192 to 521 bits) and can be programmed to execute any sequence of basic modular operations used in higher level ECC arithmetic.

Area compactness architecture for elliptic curve cryptography

- Computer Science, MathematicsInternational Conference on Pattern Recognition, Informatics and Medical Engineering (PRIME-2012)
- 2012

The scope of Montgomery ladder computationally is given and a saving of 50% on the number of gates required in implementation can be achieved, which makes ECC more attractive for high performance servers and small devices.

An Elliptic Curve Cryptosystem Design Based on FPGA Pipeline Folding

- Computer Science, Mathematics13th IEEE International On-Line Testing Symposium (IOLTS 2007)
- 2007

In this paper we present an efficient design technique for implementing the elliptic curve cryptographic (ECC) scheme in FPGAs. Our technique is based on a novel and efficient implementation of…

Architecture and Implementation of Multiplier Suitable for ECC Based on Divided Algorithm

- Computer Science, Mathematics
- 2009

This paper discusses the hardware implementation of basic serial multiplier, parallel multiplier and series-parallel multiplier in Elliptic Curve Cryptosystem(ECC) systems, and proposes an improved multiplier based on divided algorithm that reduces the total clock cycles needed.

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