FPGA Implementation of pipeline Digit-Slicing Multiplier-Less Radix 2 power of 2 DIF SDF Butterfly for Fourier Transform Structure

@article{Algnabi2012FPGAIO,
  title={FPGA Implementation of pipeline Digit-Slicing Multiplier-Less Radix 2 power of 2 DIF SDF Butterfly for Fourier Transform Structure},
  author={Yazan Samir Algnabi and Rozita Teymourzadeh and Masuri Othman and Md. Shabiul Islam},
  journal={CoRR},
  year={2012},
  volume={abs/1806.04570}
}
The need for wireless communication has driven the communication systems to high performance. However, the main bottleneck that affects the communication capability is the Fast Fourier Transform (FFT), which is the core of most modulators. This paper presents FPGA implementation of pipeline digitslicing multiplier-less radix 2 DIF (Decimation In Frequency) SDF (single path delay feedback) butterfly for FFT structure. The approach taken; in order to reduce computation complexity in butterfly… CONTINUE READING
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