Corpus ID: 18940707

FPGA Implementation of a Novel EfficientVedic FFT/IFFT Processor For OFDM

@article{John2014FPGAIO,
  title={FPGA Implementation of a Novel EfficientVedic FFT/IFFT Processor For OFDM},
  author={Nisha John and Sadan and an G.K},
  journal={International Journal of Advanced Research in Electrical, Electronics and Instrumentation Energy},
  year={2014},
  volume={3},
  pages={7964-7972}
}
  • Nisha John, Sadan, an G.K
  • Published 2014
  • Computer Science
  • International Journal of Advanced Research in Electrical, Electronics and Instrumentation Energy
Several new generation wideband data communication systems nowadays, have adopted Orthogonal Frequency division Multiplexing technique. FFT/IFFT is one of the main kernel in the OFDM system, therefore, special attention needs to be given to optimize the FFT block. Hence, utilizing low power, area efficient as well as high speed multipliers and adders in Fast Fourier Transform will ensure enhanced performance and efficiency. Urdhva Tiryakbhyam is one of the age-old Indian Vedic sutra dealing… Expand
An Area Effective OFDM Transceiver System with Multi-Radix FFT/IFFT Algorithm for Wireless Applications
An area effective Orthogonal Frequency Division Multiplexing (OFDM) transceiver design with Multi-radix FFT/IFFT algorithm is introduced for wireless applications. The Pseudo-Random Binary SequenceExpand
VLSI IMPLEMENTATION OF VARIABLE BIT RATE OFDM TRANSCEIVER SYSTEM WITH MULTI-RADIX FFT/IFFT PROCESSOR FOR WIRELESS APPLICATIONS
In this paper, a Variable Bit Rate 64 Subcarrier OFDM Transceiver system is implemented in FPGA and the Modified Multi-radix 64 point FFT/IFFT blocks present in the OFDM design is intended forExpand
FFT IMPLEMENTATION BY FPGA USING VEDIC MATHEMATICS
Fast Fourier Transform is important data processing technique in communication systems and DSP systems. In this, we propose high speed and area efficient 8 point FFT processor using Vedic algorithm.Expand
Fast Performance Pipeline Re-Configurable FFT Processor Based on Radix-22 for Variable Length N
TLDR
This paper proposes fast performance reconfigurable pipeline variable points FFT processor design for variable N points whose values can be 8, 16, 32, 64, 128, 256 and 512 sample points, which can be used for different points OFDM applications rather using different designs. Expand
High speed pipelined 64-point FFT processor based on Radix-22 for wireless LAN
This Paper presents high Speed pipeline 64-point FFT processor based on Radix-22 for wireless LAN communication systems. This method uses Radix-2 butterfly structure and Radix-22 CFA algorithm.Expand

References

SHOWING 1-10 OF 18 REFERENCES
FPGA realization of a split radix FFT processor
TLDR
The realization of a Split Radix FFT (SRFFT) processor based on a pipeline architecture reported before by the same authors is explained, to combine the higher parallelism of the 4r-FFTs and the possibility of processing sequences having length of any power of two. Expand
Efficient FPGA implementation of FFT/IFFT Processor
TLDR
The implementation of radix-2 2 single-path delay feedback pipelined FFT/IFFT processor has been developed using hardware description language VHDL on an Xc5vsx35t and simulated up to 465MHz and exhibited execution time of 0.135μS for transformation length 256-point. Expand
VLSI Implementation of 2048 Point FFT/IFFT for Mobile Wi-MAX
TLDR
Modified architecture also provides concept of local ROM module and variable length support from 128~2048 point for FFT/IFFT, and 16 bit word length with fixed point precision is used for entire implementation. Expand
FPGA based FFT algorithm implementation in WiMAX communications system
  • K. Harikrishna, T. Rao
  • Computer Science
  • 2011 2nd International Conference on Wireless Communication, Vehicular Technology, Information Theory and Aerospace & Electronic Systems Technology (Wireless VITAE)
  • 2011
TLDR
A high level implementation of a high performance FFT for OFDM Modulator and Demodulator is presented, targeted to the OFDMA based WiMAX communication modules, for increasing their efficiency by utilizing FPGA based FFT algorithm. Expand
A low logic depth complex multiplier using distributed arithmetic
TLDR
A combinatorial complex multiplier has been designed for use in a pipelined fast Fourier transform processor and a new architecture based on distributed arithmetic, Wallace-trees, and carry-lookahead adders has been developed. Expand
A high-level implementation of a high performance pipeline FFT on Virtex-E FPGAs
TLDR
The implementation results show that the implementation outperforms other implementation of FFT on the same series of FPGA, and is reported the fastest 1024-point FFT implementation on Virtex-EFPGA platform. Expand
Low-Power and Area-Efficient Carry Select Adder
  • B. Ramkumar, H. Kittur
  • Engineering, Computer Science
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 2012
TLDR
This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA, and develops and compared with the regular SQRT C SLA architecture. Expand
A new approach to pipeline FFT processor
TLDR
A new VLSI architecture for a real-time pipeline FFT processor is proposed, derived by integrating a twiddle factor decomposition technique in the divide-and-conquer approach, which has the same multiplicative complexity as the radix-4 algorithm, but retains the butterfly structure of the Radix-2 algorithm. Expand
Pipeline FFT Architectures Optimized for FPGAs
TLDR
The R22SDF was more efficient than the R4SDC in terms of throughput per area due to a simpler controller and an easier balanced rounding scheme, and it is shown that balanced stage rounding is an appropriate rounding scheme for pipeline FFT processors. Expand
Radix-4 FFT algorithms with ordered input and output data
TLDR
Two families of radix-4 factorizations for the FFT (Fast Fourier Transform) that have the property that both inputs and outputs are addressed in natural order are derived. Expand
...
1
2
...