One of the key components of memory BIST is the Address Generator (AG). In order to detect speedrelated faults, the address generator has to generate different address sequences to allow for appropriate address transitions. Its complexity is a major design issue since it requires large area and limits the BIST speed. For generating the address for Radom Accesses Memory (RAM) it requires extra hardware. If an Arithmetic and Logic Unit (ALU) uses for generating the address for RAM it reduces the hardware overhead. ALU based address generation are used in many applications like Smartcard Chips, Digital Signal Processors and Microcontrollers etc. This technique is designed by using Verilog HDL. Simulation is done to verify the functionality and synthesis is done to get the Netlist. The code is simulated and synthesized using Xilinx ISE 13.2 and the designed is implemented in SPARTAN 3E FPGA board.