FPGA Implementation of 8, 16 and 32 Bit LFSR with Maximum Length Feedback Polynomial Using VHDL

@article{Panda2012FPGAIO,
  title={FPGA Implementation of 8, 16 and 32 Bit LFSR with Maximum Length Feedback Polynomial Using VHDL},
  author={Amit Kumar Panda and Pooja J. Rajput and Balvinder Shukla},
  journal={2012 International Conference on Communication Systems and Network Technologies},
  year={2012},
  pages={769-773}
}
LFSR based PN Sequence Generator technique is used for various cryptography applications and for designing encoder, decoder in different communication channel. It is more important to test and verify by implementing on any hardware for getting better efficient result. As FPGAs is used to implement any logical function for faster prototype development, it is necessary to implement the existing design of LFSR on FPGA to test and verify the simulated & synthesis result between different lengths… CONTINUE READING
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