FPGA Implementation of 8, 16 and 32 Bit LFSR with Maximum Length Feedback Polynomial Using VHDL

  title={FPGA Implementation of 8, 16 and 32 Bit LFSR with Maximum Length Feedback Polynomial Using VHDL},
  author={Amit Kumar Panda and Pooja J. Rajput and Balvinder Shukla},
  journal={2012 International Conference on Communication Systems and Network Technologies},
LFSR based PN Sequence Generator technique is used for various cryptography applications and for designing encoder, decoder in different communication channel. It is more important to test and verify by implementing on any hardware for getting better efficient result. As FPGAs is used to implement any logical function for faster prototype development, it is necessary to implement the existing design of LFSR on FPGA to test and verify the simulated & synthesis result between different lengths… CONTINUE READING
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Publications referenced by this paper.
Showing 1-10 of 14 references

XSA-3S1000 Board V1.1

Xess Corp
User Manual. Available: http://xess.com/manuals/xsa-3S-manual-v1_1.pdf • 2007
View 2 Excerpts
Highly Influenced

Pseudorandomness and cryptographic applications

Princeton computer science notes • 1996
View 4 Excerpts
Highly Influenced

Design of Multi Bit LFSR PNRG and Performance comparison on FPGA using VHDL

K Panda Amit, P Rajput, B Shukla
International Journal of Advances in Engineering & Technology (IJAET), Mar 2012, • 2012
View 3 Excerpts

FPGA Implementation of 16 bit BBS and LFSR PN Sequence Generator: A Comparative Study

K Sewak, P Rajput, K Panda Amit
In Proce. of the IEEE Student Conference on Electrical, Electronics and Computer Sciences • 2012
View 2 Excerpts

A High-performance Pseudo-random Number Generator Based on FPGA

2009 International Conference on Wireless Networks and Information Systems • 2009
View 1 Excerpt

Efficient hardware implementation of a new pseudo-random bit sequence generator

2009 IEEE International Symposium on Circuits and Systems • 2009
View 1 Excerpt

FPGA design flow based on a variety of EDA tools

Jiang Hao, Li Zheying
in Micro-computer information, • 2007
View 2 Excerpts

Using Linear Congruential Generators for Cryptographic Purposes

Computers and Their Applications • 2005
View 1 Excerpt

On the Production of Pseudo-random Numbers in Cryptography

Jiang Hao, Li Zheying
Journal Of Changzhou Teachers College of Technology, Vo1 • 2001
View 2 Excerpts

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