FPGA Implementation of 3 / 6 SRFFT Algorithm for Length 6 * m DFTS


The Fast Fourier Transform (FFT) requires high Computational power, ability to choose the algorithm and architecture to implement it. This project explains the realization of a 3/6 FFT processor based on a pipeline architecture. The implementation has been made on a Field Programmable Gate Array (FPGA) as a way of obtaining high performance at economical… (More)

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