FPGA Implementation and Verification System of H.264/AVC Encoder for HDTV Applications

Abstract

For huge systems like video processing, FPGA prototyping plays an important role before taping out. In this paper, a verification system for H.264/AVC encoders with FPGA prototyping is proposed and implemented. An H.264 encoder with baseline profile of Level 3.2 was carried out with a clock frequency of 200MHz on a Xilinx Virtex-6 FPGA connected with DDR3 memory, which could satisfy real-time encoding for HDTV applications (720P@60fps) with a PSNR around 34 db. The encoder was finally implemented with SMIC 65nm CMOS technology for silicon verification.

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Cite this paper

@inproceedings{Wang2012FPGAIA, title={FPGA Implementation and Verification System of H.264/AVC Encoder for HDTV Applications}, author={Teng Wang and Chih-kuang Chen and Qi-Hua Yang and Xin-an Wang}, year={2012} }