FPGA Designs with Optimized Logarithmic Arithmetic


Using a general polynomial approximation approach, we present an arithmetic library generator for the logarithmic number system (LNS). The generator produces optimized LNS arithmetic libraries that improve significantly over previous LNS designs on area and latency. We also provide area cost estimation and bit-accurate simulation tools that facilitate comparison between LNS and floating-point designs.

DOI: 10.1109/TC.2010.51

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@article{Fu2010FPGADW, title={FPGA Designs with Optimized Logarithmic Arithmetic}, author={Haohuan Fu and Oskar Mencer and Wayne Luk}, journal={IEEE Trans. Computers}, year={2010}, volume={59}, pages={1000-1006} }