FPGA Based High Performance Double-Precision Matrix Multiplication

  title={FPGA Based High Performance Double-Precision Matrix Multiplication},
  author={Vinay B. Y. Kumar and Siddharth Joshi and Sachin B. Patkar and H. Narayanan},
  journal={2009 22nd International Conference on VLSI Design},
We present two designs (I and II) for IEEE 754 double precision floating point matrix multiplication, optimized for implementation on high-end FPGAs. It forms the kernel in many important tile-based BLAS algorithms, making an excellent candidate for acceleration. The designs, both based on the rank-1 update scheme, can handle arbitrary matrix sizes, and are able to sustain their peak performance except during an initial latency period. Through these designs, the trade-offs involved in terms of… CONTINUE READING
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