Extraction of geometry-related interconnect variation based on parasitic capacitance data

@article{Sun2014ExtractionOG,
  title={Extraction of geometry-related interconnect variation based on parasitic capacitance data},
  author={Li-Jie Sun and Jia Cheng and Zheng Ren and Gan-Bing Shang and Shao-Jian Hu and Shou-Mian Chen and Yu-Hang Zhao and Long Zhang and Xiao-Jin Li and Yan-Ling Shi},
  journal={IEEE Electron Device Letters},
  year={2014},
  volume={35},
  pages={980-982}
}
A new interconnect parasitic extraction flow considering geometry-related variation has been proposed in this letter. The 42 interconnect capacitance loads were fabricated by 55-nm process technology and measured to characterize geometric variation. According to the new extraction flow, interconnect technology file (ITF) has been optimized and established. As a result, both extracted error by layout parasitic extraction tool and simulated error by field solver have been improved obviously with… CONTINUE READING

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