Extended instructions for the AES cryptography and their efficient implementation


In this paper, extended instructions for the advanced encryption standard (AES) cryptography acceleration in embedded processors and efficient implementation of these instructions are presented. These AES instructions generate four elements in single-instruction, multiple-data format from each input of an AES state. The instruction count for 128-bit key AES encryption can be reduced from 688 to 340 per 128-bit block by using the proposed AES instructions. The execution unit for the AES instructions can be implemented efficiently with a single 2-Kbit table and four small multipliers. The capacity of the table has been reduced to 1/32, compared to that of a conventional fast software algorithm. The AES instructions enable embedded processors for low-cost network equipment to have cryptographic capability with minimal modification.

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@article{Nadehara2004ExtendedIF, title={Extended instructions for the AES cryptography and their efficient implementation}, author={Kouhei Nadehara and Masao Ikekawa and Ichiro Kuroda}, journal={IEEE Workshop onSignal Processing Systems, 2004. SIPS 2004.}, year={2004}, pages={152-157} }