## On Efficient Implementation of Accumulation in Finite Field Over GF(2m) and its Applications

- Pramod Kumar Meher
- IEEE Trans. VLSI Syst.
- 2009

2 Excerpts

- Published 2009 in IEEE Transactions on Computer-Aided Design of…

In this paper, we present a new approach for the extension of sequential logic functionality of <i>D</i> flip-flop in order to perform an additional Boolean function simultaneously along with its usual bit-storage function. We show that a combinational function of the form (<i>a</i> middot<i>b</i>), (<i>a</i> + <i>b</i>) , (<i>a</i> +[(<i>b</i>)]), or ([(<i>a</i>)] middot<i>b</i>) which occurs frequently in a feedforward path with a <i>D</i> flip-flop could be implemented efficiently by a <i>D</i> flip-flop with RESET or SET provision. Similarly, (<i>a</i> oplus<i>b</i>) or ((<i>a</i> middot<i>b</i>) oplus<i>c</i>) in the feedback loop with a <i>D</i> flip-flop could be implemented by a <i>T</i> flip-flop by suitable modification of the clock. The use of such extended sequential logic is found to result in a significant reduction in critical path and saving in area complexity over the direct implementation. Moreover, we present a simple approach for the construction of CMOS <i>T</i> flip-flop by modification of clock signal of <i>D</i> flip-flop, which is found to be more efficient than the <i>T</i> flip-flop derived from <i>JK</i> flip-flop. The extended sequential logic is used for the implementation of finite-field multiplication over <i>GF</i>(2<sup>m</sup>) and carry-save addition of real numbers. In both these cases, the use of extended logic is found to offer a substantial saving in area and time complexity over the conventional implementations.

@article{Meher2009ExtendedSL,
title={Extended Sequential Logic for Synchronous Circuit Optimization and Its Applications},
author={Pramod Kumar Meher},
journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
year={2009},
volume={28},
pages={469-477}
}