Corpus ID: 235446930

Exploring the Feasibility of Using 3D XPoint as an In-Memory Computing Accelerator

  title={Exploring the Feasibility of Using 3D XPoint as an In-Memory Computing Accelerator},
  author={Masoud Zabihi and Salonik Resch and M. H. Cilasun and Z. Chowdhury and Zhengyang Zhao and Ulya R. Karpuzcu and Jianping Wang and S. Sapatnekar},
This paper describes how 3D XPoint memory arrays can be used as in-memory computing accelerators. We first show that thresholded matrix-vector multiplication (TMVM), the fundamental computational kernel in many applications including machine learning, can be implemented within a 3D XPoint array without requiring data to leave the array for processing. Using the implementation of TMVM, we then discuss the implementation of a binary neural inference engine. We discuss the application of the core… Expand


Access devices for 3D crosspoint memorya)
The emergence of new nonvolatile memory (NVM) technologies—such as phase change memory, resistive, and spin-torque-transfer magnetic RAM—has been motivated by exciting applications such as storageExpand
Modeling and Signal Integrity Analysis of 3D XPoint Memory Cells and Interconnections with Memory Size Variations During Read Operation
This paper analyzed the 3D XPoint memory with memory size variation during read operation considering signal integrity (SI), and fully simulated the memory cell that consist of PCM and OTS as behavior model and the interconnections as RC model with 3D electromagnetic (EM) simulator. Expand
Exploring Performance Characteristics of the Optane 3D Xpoint Storage Technology
Intensive experiments and measurements have been carried out to extract the intrinsic performance characteristics of the Optane SSD, including the basic I/O performance behavior, advanced interleaving technology, performance consistency under a highly intensive I/o workload, and the performance impact of hybrid Optane and NAND SSD storage systems on a database application. Expand
3DICT: A Reliable and QoS Capable Mobile Process-In-Memory Architecture for Lookup-based CNNs in 3D XPoint ReRAMs
A 3D XPoint ReRAM-based process-in-memory architecture, 3DICT, is proposed to provide various test accuracies to applications with different priorities by lookup-based CNN tests that dynamically exploit the trade-off between test accuracy and latency. Expand
Analyzing the Effects of Interconnect Parasitics in the STT CRAM In-Memory Computational Platform
A methodology is developed that quantifies the way in which wire parasitics limit the size and configuration of a CRAM array and studies the impact of cell- and array-level design choices on the CRAM noise margin and determines the maximum allowableCRAM array size under various technology considerations. Expand
Device and Circuit Architectures for In‐Memory Computing
An overview of IMC in terms of memory devices and circuit architectures is provided, including typical architectures for neural network accelerators, content addressable memory (CAM), and novel circuit topologies for general‐purpose computing with low complexity. Expand
Signal Integrity Design and Analysis of 3-D X-Point Memory Considering Crosstalk and IR Drop for Higher Performance Computing
  • Kyungjune Son, Kyungjun Cho, +8 authors Joungho Kim
  • Computer Science
  • IEEE Transactions on Components, Packaging and Manufacturing Technology
  • 2020
Signal integrity (SI) is used to design and analyze 3-D X-Point memory, including a phase-change memory (PCM) cell, ovonic threshold switch (OTS) selector, interconnection lines, and peripheral circuits, including decoder, sense amplifier, and analog-to-digital converter. Expand
ASAP7: A 7-nm finFET predictive process design kit
A high density, low-power standard cell architecture, developed using design/technology co-optimization (DTCO), as well as example SRAM cells are shown, and the PDK transistor electrical assumptions are explained, as are the FEOL and BEOL design rules. Expand
A stackable cross point Phase Change Memory
A novel scalable and stackable nonvolatile memory technology suitable for building fast and dense memory devices is discussed. The memory cell is built by layering a storage element and a selector.Expand
Modeling and Verification of 3-Dimensional Resistive Storage Class Memory with High Speed Circuits for Core Operation
The modeling and verification of 3-dimensional storage class memory (SCM) is proposed using new memory with high speed circuits for core operation and the overall characteristics of memory cell model are similar with the conventional behavior model. Expand