Exploring sub-20nm FinFET design with Predictive Technology Models

@article{Sinha2012ExploringSF,
  title={Exploring sub-20nm FinFET design with Predictive Technology Models},
  author={Saurabh Sinha and Greg Yeric and Vikas Chandra and Brian Cline and Yu Cao},
  journal={DAC Design Automation Conference 2012},
  year={2012},
  pages={283-288}
}
Predictive MOSFET models are critical for early stage design-technology co-optimization and circuit design research. In this work, Predictive Technology Model files for sub-20nm multi-gate transistors have been developed (PTM-MG). Based on MOSFET scaling theory, the 2011 ITRS roadmap and early stage silicon data from published results, PTM for FinFET devices are generated for 5 technology nodes corresponding to the years 2012-2020 on the ITRS roadmap. 
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