Three-dimensional Integrated Circuits: Design, EDA, and Architecture
A new timing-driven partitioning-based placement tool for 3D FPGA integration is presented. The circuit is first divided into layers with limited number of inter-layer vias, and then placement is performed on individual layers, while minimizing the delay of critical paths. We use our tool, which will be available on the web for the research community, as a platform for exploring potential benefits in terms of delay and wire-length that 3D technologies have to offer for FPGA fabrics. We show that 3D integration results in wire-length reduction for FPGA designs. However, unlike the ASIC case, wire-length reduction does not automatically translate to much smaller circuit delays, unless multi-segment lengths are employed between layers. Our empirical analysis shows that wire-length can be reduced by up to 50% (20% on average) using 5 layers. Delay reductions are estimated to be up to 30% (15% on average) using the same number of layers.