Exploring NoC mapping strategies: an energy and timing aware technique

Abstract

Complex applications implemented as Systems on Chip (SoCs) demand extensive use of system level modeling and validation. Their implementation gathers a large number of complex IP cores and advanced interconnection schemes, such as hierarchical bus architectures or networks on chip (NoCs). Modeling applications involves capturing its computation and… (More)
DOI: 10.1109/DATE.2005.149

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@article{Marcon2005ExploringNM, title={Exploring NoC mapping strategies: an energy and timing aware technique}, author={C{\'e}sar A. M. Marcon and Ney Laert Vilar Calazans and Fernando Gehm Moraes and Altamiro Amadeu Susin and Igor M. Reis and Fabiano Hessel}, journal={Design, Automation and Test in Europe}, year={2005}, pages={502-507 Vol. 1} }