Low swing/voltage clocking is a well-studied approach to reduce dynamic power consumption in clock networks. It is, however, challenging to maintain the same performance at scaled clock voltages due to timing degradation in the Enable paths that are required for clock gating, another highly popular method to reduce dynamic power. A useful skew methodology is proposed in this paper to increase the timing slack of the Enable paths when the clock network is operating at a lower swing voltage. The skew schedule is determined via linear programming. The methodology is evaluated on five largest ISCAS’89 benchmark circuits. The results demonstrate an average 47% increase in the timing slack of the Enable path, thereby facilitating low swing operation without degrading performance.