Exploiting the on-chip inductance in high-speed clock distribution networks

@article{Ismail2001ExploitingTO,
  title={Exploiting the on-chip inductance in high-speed clock distribution networks},
  author={Yehea I. Ismail and Eby G. Friedman and Jos{\'e} Luis Neves},
  journal={IEEE Trans. VLSI Syst.},
  year={2001},
  volume={9},
  pages={963-973}
}
On-chip inductance effects can be used to improve the performance of high-speed integrated circuits. Specifically, inductance improves the signal slew rate (the rise time), virtually eliminates short-circuit power consumption and reduces the area of the active devices and repeaters inserted to optimize the performance of long interconnects. These positive effects suggest the development of design strategies that benefit from on-chip inductance. An example of a clock distribution network is… CONTINUE READING
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Designing the best clock distribution network

  • P. J. Restle, A. Duetsch
  • Proc. IEEE VLSI Circuit Symp. , June 1998, pp. 2…
  • 1998
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